There has recently been a strong demand for reductions in the size and thickness of an integrated circuit package in which semiconductor integrated circuits have been packaged. In response to such a demand, a CSP type semiconductor device is known wherein external connecting solder bumps are provided within a semiconductor chip size to attain its size reduction.
In the CSP type semiconductor device, however, there have been known so-called chipping problems that when a semiconductor wafer is divided into fractions or pieces, a semiconductor substrate is get chipped, and the semiconductor substrate is chipped upon handling of the semiconductor wafer subsequent to being divided into the pieces and completed as each of the semiconductor devices (the former will hereinafter be called “chipping at division” and the latter will hereinafter be called “chipping subsequent to completion of each semiconductor device”).
That is, in the CSP type semiconductor device divided as each piece from the semiconductor wafer after the surface of the semiconductor wafer has been resin-sealed, unlike a conventional semiconductor device resin-sealed after a semiconductor wafer has been divided into pieces, the semiconductor substrate is exposed even after the semiconductor wafer is divided into the pieces and completed as the semiconductor devices. Therefore, chipping is visually recognized even after the completion of the semiconductor device when the chipping occurs in the semiconductor substrate (around the outer edge portion of the back in particular) even at the division, thus reducing yields. Even though a semiconductor device that carries out a desired function is adopted, a product whose semiconductor substrate is chipped is bad in appearance and cannot hence be sold.
There was a possibility that even though chipping would not occur upon division, the chipping would occur in the exposed semiconductor substrate upon handling of the semiconductor device subsequent to its completion. There was particularly a high possibility that chipping would occur around the outer edge portion of the back of the exposed semiconductor substrate.
Such a solving means as shown in Japanese Patent Application Laid-Open No. 2000-260910 (patent document 1) is known to cope with such problems. That is, it is a method for forming trenches in the surface of a semiconductor wafer, sealing the surface thereof including the trenches with a resin and thereafter dividing the semiconductor wafer into pieces using a dicing blade having a thickness thinner than the width of each trench (refer to FIG. 2 in the patent document 1). According to this method, the time necessary for the dicing blade used for division to directly contact the semiconductor substrate can be less reduced because the dicing blade is not brought into direct contact with the surface of the semiconductor wafer on which stress is most applied upon its cutting but directly contacts the semiconductor substrate from the bottom of each trench. It is therefore possible to reduce a possibility that chipping at the division will occur. There is also a possibility that chipping will occur upon formation of each trench even according to this method. Since, however, the resin is charged into portions chipped with subsequent resin sealing even if the chipping occur upon trench formation, the chipping is prevented from occurring (refer to paragraphs 0014 to 0023 in the patent document 1).
Such a solving means as shown in Japanese Patent Application Laid-Open No. Hei 11(1999)-251493 (patent document 2) is next known. That is, it is a method for forming trenches in the surface and back of a semiconductor wafer respectively, sealing the surface and back thereof with a resin and thereafter dividing the semiconductor wafer into pieces using a dicing blade having a thickness thinner than the width of each trench (refer to FIGS. 37 and 36 in the patent document 2). According to the present method, since the back of a semiconductor substrate is also sealed with the resin, a possibility that chipping at the handling of a semiconductor device subsequent to its completion will occur can be reduced in addition to the advantage obtained by the method described in the patent document 1.
Next, there is known such a solving means as shown in Japanese Patent Application Laid-Open No. 2000-68401 (patent document 3). That is, it is a method for forming trenches in the surface of a semiconductor wafer and sealing the surface thereof including the trenches with a resin, and thereafter grinding the semiconductor wafer from its back to expose the trenches from its back and dividing the semiconductor wafer into pieces using a dicing blade having a thickness thinner than the width of each trench (refer to FIGS. 3 and 4 in the patent document 3). According to the present method, a possibility that chipping at the division will occur can be reduced because the dicing blade is not brought into direct contact with a semiconductor substrate upon division of the semiconductor wafer into the pieces. Since the outer peripheral portion of the back where the chipping is most likely to occur, is covered with the resin, a possibility that chipping subsequent to the completion of a semiconductor device will occur can also be reduced.
Next, there is known such a solving means as shown in Japanese Patent Application Laid-Open No. Hei 11(1999)-214434. That is, it is a method for forming trenches in the surface of a semiconductor wafer, sealing the surface thereof including the trenches with a resin, grinding the semiconductor wafer from the back of the semiconductor wafer to expose the trenches from the back thereof, and next sealing the back thereof with the resin and dividing the semiconductor wafer into pieces using a dicing blade thinner than the width of each trench (refer to FIGS. 2 and 3 in the patent document 4). According to the present method, a possibility that chipping at the division will occur can be reduced because the dicing blade is not brought into direct contact with a semiconductor substrate upon division of the semiconductor wafer into the pieces. Since the semiconductor substrate is completely covered with the resin inclusive of the back of the semiconductor substrate, it is also possible to reduce a possibility that chipping subsequent to the completion of a semiconductor device will occur.
Since, however, the semiconductor substrate (the outer edge portion of the back in particular) is exposed even after the completion of the semiconductor device according to the method described in the patent document 1, the possibility that the chipping at the handing of the semiconductor device subsequent to its completion will occur has been still left. Since the dicing blade is brought into direct contact with the semiconductor substrate upon division of the semiconductor wafer into the pieces although its contact is short in time, it cannot be said that the present method brings about complete countermeasures against the chipping at the division.
Since the dicing blade is brought into direct contact with the semiconductor substrate upon division of the semiconductor wafer into the pieces although its contact is short in time, it cannot be said that even the method described in the patent document 2 brings about complete countermeasures against the chipping at the division.
Next, the method described in the patent document 3 has a problem in that since it is necessary to provide a step for grinding the semiconductor wafer from the back thereof to expose the trenches, the number of process steps increases.
The method described in the patent document 4 has a problem in that since a step for grinding the semiconductor wafer from the back thereof to expose the trenches is needed, the number of process steps increases.